1. Field of the Invention
The present invention generally relates to R-S (reset, set) latch circuits used in logic circuitry and integrated circuits (ICs) and more particularly to a device for latching high capacitance loads quickly and efficiently.
2. Description of the Related Art
The operation of R-S latch circuits is well-known in the art and is described in "introduction to Switching Theory and Logical Design", Frederick J. Hill and Gerald R. Peterson, (2nd Ed., John Wiley & Sons, 1974). Generally, latch circuits detect a signal, or a change in a signal, and continue to produce an output after the signal terminates. The output is generally produced until a different signal (e.g., a change signal), or a change in a different signal, is detected by the circuit. Latch circuits are used to store outputs or delay outputs for controlling functions and timing within an integrated circuit.
Some latch circuits detect a change in a signal, such as when a signal goes from a relatively high level to a relatively low level, while other latch circuits detect a signal level and only operate when a signal reaches a predetermined (e.g., a specified) level. Generally, the latch circuits which detect a transition of a signal (e.g., transition signal detecting latch circuits) are more sophisticated than signal level latch circuits and are therefore larger and slower. However, transition signal detecting latch circuits are generally more desirable than signal level latch circuits because of their ability to discriminate changes in different signals.
A conventional latch circuit, as shown, for example, in U.S. Pat. No. 4,806,786 to Valentine, detects a transition in a signal, receives two inputs, a set signal and a reset signal. When the set signal transitions (e.g., goes from a relatively low signal to a relatively high signal), a specific circuit path is enabled which causes the latch circuit to output a high signal. The latch circuit will continue to produce the high signal even if the set signal transitions back to a low level. Once the latch circuit is producing a high output signal, the latch ignores the activity of the set signal and only monitors the reset signal.
When the reset signal transitions (e.g., goes from high to low), a different circuit path is enabled that causes the latch circuit to output a low level. As with the set signal, the latch circuit will continue to output the low signal irrespective of the activity of the reset signal. When the latch circuit is outputting a low level signal, the latch circuit only looks to the set signal and ignores the reset signal. As discussed above, upon a transition of the set signal, the latch circuit will modify its output.
Another conventional latch circuit is shown in U.S. Pat. No. 4,825,100 to Caspell which shows an R-S latch including an input stage, a double gate latch stage and an output stage. The input stage includes a pair of source coupled transistors, a pair of active loads and a biasing current source. The output of the input stage is coupled to the latch stage and the output stage. The latch stage includes a pair of source coupled double gate transistors and provides the latching mechanism which prevents the outputs from changing until an appropriate set or reset pulse is received.
In Caspell one pair of the gates in the latch stage are coupled to an inverted set and reset input. This pair of additional gates enables the Q and Q output to switch symmetrically, thus preventing delay between the Q and Q output.
Conventional complementary metal oxide semiconductor (CMOS) static latch circuits comprise either cross-coupled gates or cross-coupled inverters. Such circuits have asymmetric delay and/or transition times. When such circuits are used to drive large loads (e.g., such as 10-100 gates or larger), these inherent problems become worse, especially where high performance/minimum delay is important. Additional states of buffering reduce problems with asymmetry but at the cost of increased circuit delay.
The main objective of the invention is to produce high performance with large capacitive loads. Conversely, the main objective of Valentine is the produce a latch that has a small size and a small device count. The main objective of the Caspell latch is symmetric output transitions. For conventional latch circuits to drive large loads they rely upon additional stages and the circuits therefore have more devices which makes them slower.